/*
 * Copyright (C) 2024, Ingenic Semiconductor Co.,Ltd.
 * Author: Keven <keven.ywhan@ingenic.com>
 */

#ifndef __CPM_H__
#define __CPM_H__

#include <base.h>

/*
 * CPM registers offset address definition
 */
#define CPM_CPCCR_OFFSET        (0x00)  /* T41 RW 0x5500_0000 0x00 32 */
#define CPM_CPPCR_OFFSET        (0x0C)  /* T41 RW 0x5500_0000 0x00 32 */
#define CPM_CPAPCR_OFFSET       (0x10)  /* T41 APLL;RW 0x0630_5030 0x10 32 */
#define CPM_CPMPCR_OFFSET       (0x14)  /* T41 MPLL;RW 0x0630_5030 0x10 32 */
#define CPM_CPVPCR_OFFSET       (0xE0)  /* T41 VPLL;RW 0x0630_5030 0x10 32 */
#define CPM_CLKGR0_OFFSET       (0x20)  /* T41 RW 0x1F9F_FFC4 0x20 32 */
#define CPM_CLKGR1_OFFSET       (0x28)  /* T41 RW 0x0002_63FF 0x28 32 */
#define CPM_OPCR_OFFSET         (0x24)  /* T41 RW 0x0000_1500 0x24 32 */
#define CPM_DDRCDR_OFFSET	(0x2c)	/* T41 RW 0x4000_0000 0x2C 32 */
/* USB PORT 0*/
#define CPM_USBPCR_OFFSET       (0x3c)  /* T41 RW 0x4099_19B8 0x3C 32 */
#define CPM_USBRDT_OFFSET       (0x40)	/* T41 RW 0x0000_0004 0x40 32 */
#define CPM_USBVBFIL_OFFSET     (0x44)	/* T41 RW 0x00FF_0080 0x44 32 */
#define CPM_USBPCR1_OFFSET      (0x48)  /* T41 RW 0x8A80_0090 0x48 32 */
/* MSC0&MSC1 */
#define CPM_MSC0CDR_OFFSET	(0x68)	/* T41 RW 0x0010_8000 0x68 32 */
#define CPM_MSC1CDR_OFFSET	(0x6C)	/* T41 RW 0x0010_8000 0x6C 32 */
/* SFC0&SFC1 */
#define CPM_SFC0CDR_OFFSET	(0x60)	/* T41 RW 0x0000_0000 0x60 32 */
#define CPM_SFC1CDR_OFFSET	(0x7c)	/* T41 RW 0x0000_0000 0x7C 32 */
#define CPM_CPCSR_OFFSET	(0xD4)	/* T41 RO 0xF800_0000 0xD4 32 */
#define CPM_SRBC0_OFFSET	(0xC4)	/* T41 RW 0x0000_0000 0xC4 32 */

/*
* CPM registers address definition
 */
#define CPM_CPCCR        	(CPM_BASE + CPM_CPCCR_OFFSET)		/* T41 */
#define CPM_CPPCR        	(CPM_BASE + CPM_CPPCR_OFFSET)		/* T41 */
#define CPM_CLKGR0       	(CPM_BASE + CPM_CLKGR0_OFFSET)		/* T41 */
#define CPM_CLKGR1       	(CPM_BASE + CPM_CLKGR1_OFFSET)		/* T41 */
#define CPM_OPCR         	(CPM_BASE + CPM_OPCR_OFFSET)		/* T41 */
/* USB PORT 0 */
#define CPM_USBPCR       	(CPM_BASE + CPM_USBPCR_OFFSET)		/* T41 */
#define CPM_USBRDT       	(CPM_BASE + CPM_USBRDT_OFFSET)		/* T41 */
#define CPM_USBPCR1      	(CPM_BASE + CPM_USBPCR1_OFFSET)		/* T41 */

#define CPM_CPCSR        	(CPM_BASE + CPM_CPCSR_OFFSET)		/* T41 */
#define CPM_SRBC0        	(CPM_BASE + CPM_SRBC0_OFFSET)		/* T41 */
#define CPM_CPAPCR       	(CPM_BASE + CPM_CPAPCR_OFFSET)		/* T41 */
#define CPM_CPMPCR       	(CPM_BASE + CPM_CPMPCR_OFFSET)		/* T41 */
#define CPM_CPVPCR       	(CPM_BASE + CPM_CPVPCR_OFFSET)		/* T41 */
#define CPM_DDRCDR		(CPM_BASE + CPM_DDRCDR_OFFSET)		/* T41 */
/* MSC0&MSC1 */
#define CPM_MSC0CDR       	(CPM_BASE + CPM_MSC0CDR_OFFSET)		/* T41 */
#define CPM_MSC1CDR		(CPM_BASE + CPM_MSC1CDR_OFFSET)		/* T41 */
/* SFC0&SFC1 */
#define CPM_SFC0CDR		(CPM_BASE + CPM_SFC0CDR_OFFSET)		/* T41 */
#define CPM_SFC1CDR		(CPM_BASE + CPM_SFC1CDR_OFFSET)		/* T41 */

/* T41, Clock gate register 0(CLKGR0) */
#define CLKGR0_SFC0		(0x1<<21)
#define CLKGR0_UART1		(0x1<<15)
#define CLKGR0_UART0		(0x1<<14)
#define CLKGR0_MSC1		(0x1<<5)
#define CLKGR0_MSC0 		(0x1<<4)
#define CLKGR0_OTG		(0x1<<3)
/* T41, Clock gate register 1(CLKGR1) */
#define CLKGR1_SFC1   		(0x1<<12)

#define REG_CPM_CLKGR0          (*(volatile unsigned int *)CPM_CLKGR0)
#define REG_CPM_CLKGR1          (*(volatile unsigned int *)CPM_CLKGR1)

/*************** sfc clkgate config *********/
#define __cpm_start_sfc0()	(REG_CPM_CLKGR0 &= ~CLKGR0_SFC0)
#define __cpm_stop_sfc0()	(REG_CPM_CLKGR0 |= CLKGR0_SFC0)
#define __cpm_start_sfc1()	(REG_CPM_CLKGR1 &= ~CLKGR1_SFC1)
#define __cpm_stop_sfc1()	(REG_CPM_CLKGR1 |= CLKGR1_SFC1)
/******************************************/

/*************** msc clkgate config *********/
#define __cpm_start_msc0()	(REG_CPM_CLKGR0 &= ~CLKGR0_MSC0)
#define __cpm_stop_msc0()	(REG_CPM_CLKGR0 |= CLKGR0_MSC0)
#define __cpm_start_msc1()	(REG_CPM_CLKGR0 &= ~CLKGR0_MSC1)
#define __cpm_stop_msc1()	(REG_CPM_CLKGR0 |= CLKGR0_MSC1)
/******************************************/

/*************** uart clkgate config *********/
#define __cpm_start_uart0()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART0)
#define __cpm_stop_uart0()	(REG_CPM_CLKGR0 |=  CLKGR0_UART0)
#define __cpm_start_uart1()	(REG_CPM_CLKGR0 &= ~CLKGR0_UART1)
#define __cpm_stop_uart1()	(REG_CPM_CLKGR0 |=  CLKGR0_UART1)
/******************************************/

/*************** usb/otg clkgate config *********/
#define __cpm_start_otg()	(REG_CPM_CLKGR0 &= ~(CLKGR0_OTG))
#define __cpm_stop_otg()	(REG_CPM_CLKGR0 |= (CLKGR0_OTG))
/******************************************/

#endif /* __CPM_H__ */
